In semiconductor processing, processing techniques can be used to decrease package size of semiconductor devices. Generally in package processing, semiconductor dies are placed active surface side down on an adhesive material situated on a process carrier substrate, and encapsulated with a molding material, which is then cured. The molding material can be any appropriate encapsulant, for example, a silica-filled epoxy molding compound, a plastic encapsulation resin, or other polymeric material such as silicones, polyimides, phenolics and polyurethanes. The encapsulated die panel is then separated from the adhesive material and process carrier substrate and cleaned to remove any remaining adhesive. Additional processing can then be conducted on the exposed surface of the dies to build-up a multi-layer circuit interconnect. An interconnect is generally composed of alternating layers of an insulating or dielectric material and metal (e.g., traces, interconnects, etc.). The interconnect is typically formed using photolithography and plating techniques. Solder balls can be formed or dropped on solder ball pads formed in a final metallization layer, for making electrical connections to a PCB. The dies can then be singulated by cutting through designated areas to form single or multiple semiconductor device packages.
Solder ball pads are formed on a semiconductor die to provide means for transferring electrical signals and power to and from circuitry of the semiconductor die through solder balls, conductive bumps, etc. In a multilayered circuit interconnect, an insulative layer or solder mask (also called a passivation layer) is formed over the final metallization layer that has been laminated or formed on an insulating layer. The final metallization layer typically includes solder ball pads, circuit traces, through-hole vias, etc. An opening is formed in the solder mask to expose a portion of the solder ball pad and a solder ball may be attached or formed on the exposed pad area. In semiconductor processing, it is important to have a good connection and adhesion of metal layers and insulating layers to prevent cracking of the insulating layers which can reduce package integrity and reliability and lead to chip failure.